1. Field of the Invention
This invention relates to the testing of integrated circuits, and in particular, to a method and apparatus for testing integrated circuits in an efficient manner.
2. Discussion of the Related Art
Due to improper manufacturing, integrated circuits (ICs) are subject to a variety of failure modes. Therefore, proper testing of ICs during and after fabrication is important to improving the reliability and yield of product shipped to customers. However, the costs associated with testing ICs are growing rapidly.
Overall cost is a significant factor in the success of integrated circuit products. Testing ICs is a relatively time-consuming and expensive process. Therefore, it is desirable to keep testing costs low by minimizing test throughput times.
Even though many techniques and software tools are becoming available to increase design productivity, test productivity lags far behind. Poor test productivity means that the design cycle may soon be dominated by the testing activities. In addition, the complexity of ICs requires relatively expensive testing equipment.
As electronic technology improved, testers became faster than the handlers which supplied them. The time required for testing ICs continues to decline. As a result, testers often operate only a fraction of their test time capability because the handler is unable to deliver and transport ICs to the tester as fast as the tester is able to evaluate them. This results in inefficient use of the tester as the tester remains idle while the handler transports ICs.
For example, FIG. 1 illustrates a prior art device testing station 10. Device testing station 10 includes test instruments for testing ICs. Such device testing stations are available on the open market as known in the art, and can be, for example, the MCT 2010 tester. Other models are available from the same manufacturer and other manufacturers, and are suited for use with the present invention as will become apparent to those skilled in the art.
Referring to FIG. 1, in its normal configuration, as provided by the manufacturer, device testing station 10 includes a controller 16, a keyboard 18, a power supply 20, an auxiliary blower 22, a test head 14, and a single site loadboard 12. The test head 14 is designed to interface with other test equipment such as a device handler (not shown). The power supply 20 and the controller 16 are connected to test head 14 by a hose assembly 26 that transfers cooling air, digital signals, and power between them. As a complete device testing station, controller 16, keyboard 18, power supply 20, and auxiliary blower 22, are in a vertical rack-mount cabinet 28. Test head 14 is supported by a test head stand 24.
Single site loadboard 12 interfaces with test head 14. Single site loadboard 12 provides a single test site 13 for testing a device. Therefore, device testing station 10 can only be used for single site testing. Single site testing represents a very inefficient use of an expensive device testing station.
However, modifying a tester so that it is capable of testing multiple high pin count devices is an expensive undertaking. For example, testers such as the MCT 2010 provide up to 64 pin electronics cards (pin cards). Testing ICs requires that each device pin be assigned to one pin card. As a result, testing an IC with 56 pins requires 56 pin cards. Therefore, in order to test two ICs each with 56 pins without incurring all of the time delay associated with unloading the first IC and loading the second IC would require a tester with at least 112 pin cards and, as a result, would require the addition of complex and expensive equipment.
Accordingly, it would be desirable to provide a method and apparatus for testing ICs that maximizes the use of a tester without requiring additional complex and expensive equipment.